芯耀
88
名稱：8位全減器設(shè)計Verilog代碼Quartus仿真
軟件：Quartus
語言：Verilog
代碼功能：
給出1位全減器的 Verilog HDL描述。
要求：
1)首先設(shè)計1位半減器,然后用例化語句將它們連接起來,圖中 h_ suber是半減器,diff是輸出差,Sout是借位輸出, sub_in是借位輸入。
2)根據(jù)圖設(shè)計1位全減器。
3)以1位全減器為基本硬件,構(gòu)成串行借位的8位全減器,要求用例化語句來完成此項設(shè)計。
(1)將RTL代碼復(fù)制黏貼到下面
(2)將 testbench仿真測試代碼復(fù)制黏貼在下方
(3)截圖波形,波形能夠清晰反映所有變量的變化情況
(4)截圖RTL視圖
FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com
演示視頻：
設(shè)計文檔：
module f_suber_8bit(
input [7:0]x,
input [7:0]y,
input sub_in,
output [7:0]diff,
output sub_out
);
wire sub_out1;
wire sub_out2;
wire sub_out3;
wire sub_out4;
wire sub_out5;
wire sub_out6;
wire sub_out7;
f_suber i0_f_suber(
. x(x[0]),
. y(y[0]),
. sub_in(sub_in),
. diff(diff[0]),
. sub_out(sub_out1)
);
f_suber i1_f_suber(
. x(x[1]),
. y(y[1]),
. sub_in(sub_out1),
. diff(diff[1]),
. sub_out(sub_out2)
);
f_suber i2_f_suber(
. x(x[2]),
. y(y[2]),
. sub_in(sub_out2),
. diff(diff[2]),
. sub_out(sub_out3)
);
f_suber i3_f_suber(
. x(x[3]),
. y(y[3]),
. sub_in(sub_out3),
. diff(diff[3]),
. sub_out(sub_out4)
);
f_suber i4_f_suber(
. x(x[4]),
. y(y[4]),
. sub_in(sub_out4),
. diff(diff[4]),
. sub_out(sub_out5)
);
f_suber i5_f_suber(
. x(x[5]),
. y(y[5]),
. sub_in(sub_out5),
. diff(diff[5]),
. sub_out(sub_out6)
);
f_suber i6_f_suber(
. x(x[6]),
. y(y[6]),
. sub_in(sub_out6),
. diff(diff[6]),
. sub_out(sub_out7)
);
f_suber i7_f_suber(
. x(x[7]),
. y(y[7]),
. sub_in(sub_out7),
. diff(diff[7]),
. sub_out(sub_out)
);
endmodule
Testbench代碼
module testbench();
reg [7:0]x;
reg [7:0]y;
reg sub_in;
wire [7:0]diff;
wire sub_out;
f_suber_8bit i_f_suber_8bit(
.x(x),
.y(y),
.sub_in(sub_in),
.diff(diff),
.sub_out(sub_out)
);
initial begin
x=0;
y=0;
sub_in=0;
#10;
x=7;
y=5;
sub_in=1;
#10;
x=89;
y=28;
sub_in=0;
#10;
x=45;
y=25;
sub_in=1;
#10;
x=44;
y=45;
sub_in=0;
#10;
x=78;
y=42;
sub_in=0;
#10;
end
endmodule
仿真圖
RTL圖
部分代碼展示:
module?f_suber( input?x, input?y, input?sub_in, output?diff, output?sub_out ); wire?diff1; wire?s_out1; wire?s_out2; h_suber?i1_h_suber( .?x(x), .?y(y), .?diff(diff1), .?s_out(s_out1) ); h_suber?i2_h_suber( .?x(diff1), .?y(sub_in), .?diff(diff), .?s_out(s_out2) ); assign?sub_out=?s_out1?|?s_out2; endmodule
點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=590
