波形發(fā)生器設(shè)計VHDL代碼Quartus 21EDA-CPLD開發(fā)板

名稱：波形發(fā)生器設(shè)計VHDL代碼Quartus? 21EDA-CPLD開發(fā)板

軟件：Quartus

語言：VHDL

代碼功能：

信號發(fā)生器設(shè)計

信號發(fā)生器由波形選擇開關(guān)控制波形的輸岀,分別能輸出正弦波、方波和三角波三種波形,波形的周期為2秒(由40M有源晶振分頻控制)。考慮程序的容量,每種波形在一個周期內(nèi)均取16個取樣點,每個樣點數(shù)據(jù)是8位(數(shù)值酒范:00000000~11111111)要求將D/A變換前的8位二進(jìn)制數(shù)據(jù)(以十進(jìn)制方式)輸出到數(shù)碼管動態(tài)演示出來。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

本代碼已在21EDA-CPLD開發(fā)板驗證，21EDA-CPLD開發(fā)板如下，其他開發(fā)板可以修改管腳適配：

演示視頻：

設(shè)計文檔：

1.工程文件

2.程序文件

3.程序運行

4.RTL圖

5.管腳分配

6.仿真文件

7.程序仿真圖

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?wave_generation?IS
???PORT?(
??????sys_clk?????????:?IN?STD_LOGIC;--輸入時鐘????
??????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--波形選擇
??????SEL?????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)碼管位選
??????SEG?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選
???);
END?wave_generation;
ARCHITECTURE?behaviour?OF?wave_generation?IS
--分頻模塊，分頻到8Hz
COMPONENT?div_8Hz?IS
???PORT?(
??????clk_in??:?IN?STD_LOGIC;--50MHz輸入
??????clk_8Hz??:?OUT?STD_LOGIC--8Hz輸出
???);
END?COMPONENT;
???--波形發(fā)生模塊
COMPONENT?carrier_wave?IS
??????PORT?(
?????????clk?????????????:?IN?STD_LOGIC;
?????????triangular_wave?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
--3選1模塊，00輸出0;01-方波;10-三角波;11-正弦波，wave_select控制3選1
COMPONENT?MUX_31?IS
???PORT?(
?????????triangular_wave?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????square_wave?????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????sin_wave????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);
?????????wave_data???????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--波形輸出
???);
END?COMPONENT;
--顯示模塊
COMPONENT?display?IS
???PORT?(
??????clk????????????:?IN?STD_LOGIC;
??????wave_data??????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--波形
??????SEL?????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)碼管位選
??????SEG?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選
???);
END?COMPONENT;
???SIGNAL?wave_data:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?triangular_wave???:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?square_wave?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?sin_wave????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
SIGNAL?clk_8Hz????????:?STD_LOGIC;
BEGIN
--分頻模塊，分頻到8Hz
div_8Hz_U:div_8Hz
???PORT?MAP(
??????clk_in=>sys_clk,--50MHz輸入
??????clk_8Hz=>clk_8Hz--8Hz輸出
???);
???
???--波形產(chǎn)生模塊
???carrier_wave_ge?:?carrier_wave
??????PORT?MAP?(
?????????clk??????????????=>?clk_8Hz,
?????????triangular_wave??=>?triangular_wave,
?????????square_wave??????=>?square_wave,
?????????sin_wave?????????=>?sin_wave
??????);

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=560